SPI Master/Slave Interface

in the master_tx_fifo process i've added delay between di_req and wren_m. see below added code (last 5 line are mine) as result the wren occur when the master state machine value is 1. A new transaction does start. however, the sck_ena_reg is low during this transaction, and the SPI clock is disabled.

master_tx_fifo_proc: process is variable fifo_memory : fifo_memory_type := (X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789", X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead"); variable fifo_head : integer range 0 to fifo_memory_size-1; begin -- synchronous rst_i wait until rst = '1'; wait until m_clk'event and m_clk = '1'; di_m '0'); wren_m fifo_head := 0; wait until rst = '0'; wait for 200 ns; wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge -- wait until di_req_m = '1'; -- wait shift register request for data -- load next fifo contents into shift register for cnt in 0 to (fifo_memory_size/2)-1 loop fifo_head := cnt; -- pre-compute next pointer wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge di_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge wren_m wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge wren_m wait until di_req_m = '1'; -- wait shift register request for data if cnt=1 then for i in 1 to 20 loop wait until m_clk'event and m_clk = '1'; end loop; end if;

Thanks! I will look into this behaviour and comment on it.

• Jonny