SPI Master/Slave Interface

Hi, Thanks for the great tool. I'm a newbie at FPGA stuff, so I'm not sure how to approach this.

After many transfers (a few hours of running) moving data between a CPU and an FPGA using the SPI_SLAVE module, I find events where a few bits get missed. This means that SPI no longer works. Is there some way to reset the spi slave?

(I could reset the entire device, but I'm having a bugger of a time understanding the JTAG interface, so I'm not sure how to do it.)

Thanks for any advice.