OpenCores

SPI Master/Slave Interface

Issue List
Single clock #2
Closed jdoin opened this issue over 8 years ago— assigned to: jdoinReminder
jdoin commented over 8 years ago

<reminder to self> Change SPI clock generation, that now is a clock divider, to a clock-enable structure, keeping a single high-speed clock for the core. This will streamline GCLK buffers for the whole design, and may improve max frequency.

jdoin was assigned over 8 years ago
jdoin commented over 8 years ago

Changed internal clocking to use one single high-speed clock for the entire serial section, using clock enables to synchronize lower rate functions. This will preserve global clocking resources and reduce route delay clock glitches, increasing design safety. The new version was verified in silicon with a 100MHz Atlys board, at 8.333MHz, 10MHz, 12.5MHz, 16.666MHz and 25MHz SPI clocks, with no glitches.

jdoin commented over 8 years ago

Adjusted the SCK clock phase to the MOSI update edge, using one pipeline delay on SCK. Now the spi_master can go over 100MHz of spi line clock if using only MOSI. The new version was verified at 50MHz SPI on the Atlys board (Spartan-6 @ 100MHz).

jdoin closed this over 8 years ago
jdoin commented about 8 years ago

The spi_slave.vhd was redesigned in v2.00.0110, and now both master and slave cores were verified at 100MHz. The master interface takes only one high-speed system clock and uses clock enables for all sequential logic.