SPI Master/Slave Interface

The CPHA='1' setup results in a SCK glitch at the end of the last word, causing an extra clock pulse on the bus.

in v1.12.0105, SPI_MASTER.VHD changed to fix the SCK glitch. When CPHA='1', the maximum operation speed is 25MHz for spi SCK. When CPHA='0', top speed is +50MHz.

Currently, the models at SVN (v1.12.0105) are NOT to be used with CPHA='1'. All use cases with CPHA='0' are tested and run perfectly in silicon and in the simulator. I'm working on the CPHA='1' design issue, and will update as soon as I have a better solution.

in SPI_MASTER.VHD v1.13.0125 the CPHA='1' is fixed. The core was verified in FPGA silicon at 50MHz of SPI clock. I'm now working at the SPI_SLAVE.VHD code, in the CPHA='1' logic. The SVN files will be updated today with the current master core.

The logic for SPI_SLAVE clocking was redesigned to address the CPHA='1' cases. MISO output is updated one half-cycle before data shifting, and parallel data out is updated at the last SCK bit edge of each word. This solved for all CPHA cases without increasing generated logic footprint.

The resulting core is still a CLB-pure implementation, and both cores now go up to 100MHz. This was tested in hardware using a Spartan-6 Atlys board.