The cores allow continuous transfer mode without any sck pauses. The slave core was not tested in silicon for the CT mode, but only in simulation.
The master and slave cores CT logic were verified in simulation, and minor adjusts were made to make the 'do_valid', 'wr_ack', and 'di_req' signals to have the same behavior for both cores.
A bug in the phasing for the slave core caused wrong transmission/sampling of data at opposing cpol/cpha polarities. The bug is fixed, and general timing controlled by the FSM was adjusted. Both cores are tested at all SPI modes, for single and continuous transfers, at 50MHz spi line clock.
The cores are delivered, ready to be used.