SPI Master/Slave Interface

The spi_slave.vhd has a MUX at the MISO output that preloads the top bit of the shifter before any spi clock. BUG: the mux will glitch when CPHA='1' at the first clock edge.

The glitch was due to using SSEL as the MUX selector, and when SSEL went LOW miso was updated at the first clock edge, the wrong edge for CPHA='1'.<br/> <br/> At the scope screen below, the 1st word transferred is 0x51.<br/> We can see the miso preload to '0', and the update to '1' taking place at the correct clock edge:<br/><br/> <img src="usercontent,img,1314589018" alt="slave_top_bit_preload" title="slave miso preload" /> <br/>