SystemC/Verilog Random Number Generator

This module repeats after only a few hundred million iterations. Worse, the LFSR makes a small repeating sequence in the middle bits when you begin with the reset value of 1. The verilog codding is in error and it looks like the author did not understand how verilog registers and clocking actually function. Here is the code of what I believe the author intended to as this correction make really random noise beginning with any seed, even 1. (except 0...):

//CASR: reg36:0 CASR_varCASR; always @(posedge clk ) begin

if ( rst ) CASR_varCASR <= (1); else begin

     if (ena) begin
     CASR_varCASR [36]<=CASR_varCASR [35]^CASR_varCASR [0];
     CASR_varCASR [35]<=CASR_varCASR [34]^CASR_varCASR [36];
     CASR_varCASR [34]<=CASR_varCASR [33]^CASR_varCASR [35];
     CASR_varCASR [33]<=CASR_varCASR [32]^CASR_varCASR [34];
     CASR_varCASR [32]<=CASR_varCASR [31]^CASR_varCASR [33];
     CASR_varCASR [31]<=CASR_varCASR [30]^CASR_varCASR [32];
     CASR_varCASR [30]<=CASR_varCASR [29]^CASR_varCASR [31];
     CASR_varCASR [29]<=CASR_varCASR [28]^CASR_varCASR [30];
     CASR_varCASR [28]<=CASR_varCASR [27]^CASR_varCASR [29];
     CASR_varCASR [27]<=CASR_varCASR [26]^CASR_varCASR [27]^CASR_varCASR [28];
     CASR_varCASR [26]<=CASR_varCASR [25]^CASR_varCASR [27];
     CASR_varCASR [25]<=CASR_varCASR [24]^CASR_varCASR [26];
     CASR_varCASR [24]<=CASR_varCASR [23]^CASR_varCASR [25];
     CASR_varCASR [23]<=CASR_varCASR [22]^CASR_varCASR [24];
     CASR_varCASR [22]<=CASR_varCASR [21]^CASR_varCASR [23];
     CASR_varCASR [21]<=CASR_varCASR [20]^CASR_varCASR [22];
     CASR_varCASR [20]<=CASR_varCASR [19]^CASR_varCASR [21];
     CASR_varCASR [19]<=CASR_varCASR [18]^CASR_varCASR [20];
     CASR_varCASR [18]<=CASR_varCASR [17]^CASR_varCASR [19];
     CASR_varCASR [17]<=CASR_varCASR [16]^CASR_varCASR [18];
     CASR_varCASR [16]<=CASR_varCASR [15]^CASR_varCASR [17];
     CASR_varCASR [15]<=CASR_varCASR [14]^CASR_varCASR [16];
     CASR_varCASR [14]<=CASR_varCASR [13]^CASR_varCASR [15];
     CASR_varCASR [13]<=CASR_varCASR [12]^CASR_varCASR [14];
     CASR_varCASR [12]<=CASR_varCASR [11]^CASR_varCASR [13];
     CASR_varCASR [11]<=CASR_varCASR [10]^CASR_varCASR [12];
     CASR_varCASR [10]<=CASR_varCASR [9] ^CASR_varCASR [11];
     CASR_varCASR [9] <=CASR_varCASR [8] ^CASR_varCASR [10];
     CASR_varCASR [8] <=CASR_varCASR [7] ^CASR_varCASR [9];
     CASR_varCASR [7] <=CASR_varCASR [6] ^CASR_varCASR [8];
     CASR_varCASR [6] <=CASR_varCASR [5] ^CASR_varCASR [7];
     CASR_varCASR [5] <=CASR_varCASR [4] ^CASR_varCASR [6];
     CASR_varCASR [4] <=CASR_varCASR [3] ^CASR_varCASR [5];
     CASR_varCASR [3] <=CASR_varCASR [2] ^CASR_varCASR [4];
     CASR_varCASR [2] <=CASR_varCASR [1] ^CASR_varCASR [3];
     CASR_varCASR [1] <=CASR_varCASR [0] ^CASR_varCASR [2];
     CASR_varCASR [0] <=CASR_varCASR [36]^CASR_varCASR [1];
     end
  end

end //LFSR: reg42:0 LFSR_varLFSR; always @(posedge clk) begin

if ( rst ) LFSR_varLFSR <= (1); else begin

     if (ena) begin

     LFSR_varLFSR [42]<=LFSR_varLFSR [41];
     LFSR_varLFSR [41]<=LFSR_varLFSR [40]^LFSR_varLFSR [42] ;
     LFSR_varLFSR [40]<=LFSR_varLFSR [39];
     LFSR_varLFSR [39]<=LFSR_varLFSR [38];
     LFSR_varLFSR [38]<=LFSR_varLFSR [37];
     LFSR_varLFSR [37]<=LFSR_varLFSR [36];
     LFSR_varLFSR [36]<=LFSR_varLFSR [35];
     LFSR_varLFSR [35]<=LFSR_varLFSR [34];
     LFSR_varLFSR [34]<=LFSR_varLFSR [33];
     LFSR_varLFSR [33]<=LFSR_varLFSR [32];
     LFSR_varLFSR [32]<=LFSR_varLFSR [31];
     LFSR_varLFSR [31]<=LFSR_varLFSR [30];
     LFSR_varLFSR [30]<=LFSR_varLFSR [29];
     LFSR_varLFSR [29]<=LFSR_varLFSR [28];
     LFSR_varLFSR [28]<=LFSR_varLFSR [27];
     LFSR_varLFSR [27]<=LFSR_varLFSR [26];
     LFSR_varLFSR [26]<=LFSR_varLFSR [25];
     LFSR_varLFSR [25]<=LFSR_varLFSR [24];
     LFSR_varLFSR [24]<=LFSR_varLFSR [23];
     LFSR_varLFSR [23]<=LFSR_varLFSR [22];
     LFSR_varLFSR [22]<=LFSR_varLFSR [21];
     LFSR_varLFSR [21]<=LFSR_varLFSR [20];
     LFSR_varLFSR [20]<=LFSR_varLFSR [19]^LFSR_varLFSR [42] ;
     LFSR_varLFSR [19]<=LFSR_varLFSR [18];
     LFSR_varLFSR [18]<=LFSR_varLFSR [17];
     LFSR_varLFSR [17]<=LFSR_varLFSR [16];
     LFSR_varLFSR [16]<=LFSR_varLFSR [15];
     LFSR_varLFSR [15]<=LFSR_varLFSR [14];
     LFSR_varLFSR [14]<=LFSR_varLFSR [13];
     LFSR_varLFSR [13]<=LFSR_varLFSR [12];
     LFSR_varLFSR [12]<=LFSR_varLFSR [11];
     LFSR_varLFSR [11]<=LFSR_varLFSR [10];
     LFSR_varLFSR [10]<=LFSR_varLFSR [9];
     LFSR_varLFSR [9] <=LFSR_varLFSR [8];
     LFSR_varLFSR [8] <=LFSR_varLFSR [7];
     LFSR_varLFSR [7] <=LFSR_varLFSR [6];
     LFSR_varLFSR [6] <=LFSR_varLFSR [5];
     LFSR_varLFSR [5] <=LFSR_varLFSR [4];
     LFSR_varLFSR [4] <=LFSR_varLFSR [3];
     LFSR_varLFSR [3] <=LFSR_varLFSR [2];
     LFSR_varLFSR [2] <=LFSR_varLFSR [1];
     LFSR_varLFSR [1] <=LFSR_varLFSR [0]^LFSR_varLFSR [42] ;
     LFSR_varLFSR [0] <=LFSR_varLFSR [42];

     end
  end

end

//combinate: always @(posedge clk) begin if ( rst ) number_o <= (0); else if (ena) number_o <= (LFSR_varLFSR 31:0^CASR_varCASR31:0); end endmodule

Please excuse the missing carriage in my above post. Something went wrong with the copy & paste.

Here is is really cleaned up...

module rnd ( clk, rst, ena, load, seed, out );

input clk, rst, ena, load; input 31:0 seed ; output reg 31:0 out ;

reg36:0 CASR; reg42:0 LFSR; always @(posedge clk ) begin

if ( rst ) begin

                CASR  <= (37'h1);  // Random starting point.
                LFSR  <= (43'h1); // Random starting point.

end else if (load) begin

                CASR  <= 37'(seed) | 33'h100000000 ; // Load seed, protect from a seed of 0.
                LFSR  <= 43'(seed) | 33'h100000000 ; // Load seed, protect from a seed of 0.

end else if (ena) begin

                CASR[36:0] <= ( {CASR[35:0],CASR[36]} ^ {CASR[0],CASR[36:1]} ^ CASR[27]<<27 ) ;
                LFSR[42:0] <= ( {LFSR[41:0],LFSR[42]} ^ LFSR[42]<<41 ^ LFSR[42]<<20 ^ LFSR[42]<<1 ) ;

                out [31:0] <= ( LFSR [31:0] ^ CASR[31:0] );

end

end endmodule

Why do the carriage returns keep on disappearing?