OpenCores

SystemC/Verilog Random Number Generator :: Overview



Project maintainers

Details

Name: systemc_rng
Created: Aug 19, 2004
Updated: Jan 9, 2019
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star3you like it: star it!

Other project properties

Category:Other
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statistical properties. Based on the Thomas E. Tkacik at CHES 2002 work. For more information in spanish visit vhdl.es

Features

- Very good statisticall properties
- Synthesizable

Status

- Done