Affected releases: 0.5 BETA, 0.6 BETA, 0.6.1 BETA
PROG is deasserted in XTAL2 cycle which might lead to read data being already invalid (tri-stated) when the core samples P23:0 at the end of XTAL3.
Fixed in: clock_ctrl.vhd 1.12 Fix will be included in next release.