T48 µController

Maybe a Wishbone interface would enhance the usability of the core. It is yet unclear how the architecture of such an interface could look like due to the fixed nature of the external access scheme.

Initial idea:

• Core posts read / write request to Wishbone controller
• Controller signals "transfer complete" via interrrupt

Wishbone master interface is now available from CVS. It is used in the new sample system t8050_wb. Both will be part of the next release.