T48 µController
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A #9
Closed arniml opened this issue about 20 years ago
arniml commented about 20 years ago
Affected releases: 0.1 BETA, 0.2 BETA, 0.3 BETA, 0.4 BETA
The control signals RD' and WR' are not asserted when the instructions INS A, BUS and OUTL BUS, A are executed. The BUS is read or written but the control signals are missing.
Fixed in: decoder.vhd 1.16 Fix will be included in next release.
arniml was assigned about 20 years ago
arniml closed this about 20 years ago
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