T65 CPU

Hi, i'll try to describe the bug I think I might have found.

This bug was reported for revision 14.

-- First of all, I think we should always use * as sensitivity list -- It is better for synthesis and we won't have any problem if we -- forget something process (P_In, BusA, BusB) variable AL : unsigned(6 downto 0); variable AH : unsigned(6 downto 0); variable C : std_logic; begin AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);

-- pragma translate_off if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on

if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
	ADC_Z <= '1';
else
	ADC_Z <= '0';
end if;

-- A comment is needed here, you should say why +6
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
	AL(6 downto 1) := AL(6 downto 1) + 6;
end if;

-- AL(6) is zero
-- it has never and will never be 1
C := AL(6) or AL(5);
-- In this manner C := AL(5)

AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);

-- Negative Flag
ADC_N <= AH(4);

-- oVerflow Flag
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));

-- pragma translate_off if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; -- pragma translate_on

if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
	AH(6 downto 1) := AH(6 downto 1) + 6;
end if;

-- same problem here
-- AH(6) is zero.
-- it has never and will never be 1
ADC_C <= AH(6) or AH(5);

ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));

end process;

You can close this!

my bad...

In fact, it is not a bug! but the code have no comments at all...