Wallner, Daniel

MikeJ

T65 CPU

It would be great if you could update this repository with fixes made by the FPGAArcade and PaceDev projects.

The most recent version I'm aware of is Mark McDougall's fix to the B flag handling: his version is found at https://svn.pacedev.net/repos/pace/sw/src/component/cpu/t65/
(ignore the invalid certificate) and incorporates other fixes from FPGAArcade.

Two 'if' clauses from line 374 in T65.vhd are replaced with
  {{{
  -- B=1 always on the 6502
  P(Flag_B) <= '1';
  if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
    if MCycle = "011" then
      -- B=0 in *copy* of P pushed onto the stack
      P(Flag_B) <= '0';
    elsif MCycle = "100" then
      P(Flag_I) <= '1';
    end if;
  end if;
}}}

Thanks!

B flag: fixed elsewhere

Hi, i'll try to describe the bug I think I might have found.

This bug was reported for revision 14.

-- First of all, I think we should always use * as sensitivity list
-- It is better for synthesis and we won't have any problem if we
-- forget something
process (P_In, BusA, BusB)
	variable AL : unsigned(6 downto 0);
	variable AH : unsigned(6 downto 0);
	variable C : std_logic;
begin
	AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
	AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);

-- pragma translate_off
	if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
	if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on

	if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
		ADC_Z <= '1';
	else
		ADC_Z <= '0';
	end if;

	-- A comment is needed here, you should say why +6
	if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
		AL(6 downto 1) := AL(6 downto 1) + 6;
	end if;

	-- AL(6) is zero
	-- it has never and will never be 1
	C := AL(6) or AL(5);
	-- In this manner C := AL(5)

	AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);

	-- Negative Flag
	ADC_N <= AH(4);

	-- oVerflow Flag
	ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));

-- pragma translate_off
	if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on

	if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
		AH(6 downto 1) := AH(6 downto 1) + 6;
	end if;

	-- same problem here
	-- AH(6) is zero.
	-- it has never and will never be 1
	ADC_C <= AH(6) or AH(5);

	ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;

ADC and SBC

Hi there,

I`ve found no documentation at all. Internet research is not an answer because it can`t explain internal signals from your code for example. the project started years ago... now it can be too late to remember what you`ve written.

Best Regards
Gabriel Oshiro

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T65 CPU