Hello, I tried to simulate this project, but got simulation runtime error: Failed to open readmem file "Instructions.mem" in read mode.

No such file or directory. (errno = ENOENT) : TestBench_THEIA.v(214)

Also got this warning: ** Warning: (vsim-PLI-3407) Too many data words read on line 65541 of file "Textures.mem". (Current address 196609, address range 0:196608) : TestBench_THEIA.v(212)

Time: 0 ps Iteration: 0 Instance: /TestBench_Theia

Hi there, I forgot to upload this file in the first example. Good you pointed this out. I will upload the file ASAP.

Hi there, I forgot to upload this file in the first example. Good you pointed this out. I will upload the file ASAP.

I just uploaded the file to SVN under the exmaple1 folder. The reason why I forgot is probably because the examples still uses the code in ROM.

Please copy the file into the simulation executable directory and let me know if are able to simulate. Thanks for your patience.

-D

Thanks a lot for the fast response. Right now I am able to simulate this design, but unfortunetely it won't work in several simulators (for example MTI65-Actel edition). I debugged it a little and found, that it depends on process execution order. I have fixed it in testbench component so it started working in another simulator, but MTI still won't simulate it properly. Have you idea what could be wrong ? I try to send you my changes if you are interested in.

Hi, I haven't really tested the RTL in other simulators. I have simulated with success under the free available isim simulator from Xilinx. You can refer to the readme file under the testbench directory to create a Xilinx project. Regarding modelsim, I am interested in looking at your changes in the testbench, maybe this way we can figure out a what is making it fail for modelsim.

One final question, you mentioned you were able to make it work for another simulator, which simulator was that? Where you able to see the final render image in the example?

Thanks a lot for you interest. -D

Hi Diego, Sorry for long delay, but I was very busy at work and had no time to prepare my changes and send them to you. I am using Synapicad's Verilogger Extreme simulator (available with whole debugging, testbench generation IDE called Testbencher. It also can be downloaded for free evaluation so you can try it if you want... Is your opencores email valid & active ? I would like to send you my changes - actually tried to commit but it failed because no rights, what didn't supprise me :-)

Hi, You can send the files to my gmail account: diego.valverde.g 'at' gmail.com or I can add you to the project so can check files in, if you want.

You mentioned you were able to make it work for another simulator, which simulator was that? Where you able to see the final render image in the example?

Thanks a lot. -D