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out is a reserved keywork for VHDL #4
Open fpgausr opened this issue over 5 years ago
fpgausr commented over 5 years ago

Aes_256 (and possibly the others) make use of name "out" as port name of the encrypted data bus coming out the verilog module.

The name "out" is a reserved keywork in VHDL so when you put an instance of the verilog core inside a VDHL top you get the below error. near "out": (vcom-1576) expecting IDENTIFIER.

To fix the bug is that easy to rename out to something else like dout. Thanks


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