Homer Xing

I was working with the core and trying out decryption with some sample test vectors, however I cant seem to get the right output out of the core. Is there some sort of modification that I need to do in order to be able to decrypt with it or is there a specific process that anyone can provide me with for how to run about using decryption? Thanks!

AES Decryption

Hi my name is John, currently I am doing a final year project called AES using Verilog in my final year course which is Electronic Engineering, I have already studied all the transformations in encryption and decryption processes but I still cannot figure out how to code it due to my verilog base not strong enough but I really interested that how you code the way that AES performs and one of the reason why I want to do such a project is because of I think privacy is very important to all of us and VLSI is very interesting so that i choose it as my major course between Electrical and Electronic paths. I would really appreciate that if I have that pleasure to get the source code of AES from you so that I can learn more and more in verilog base. :D

AES Code

In the testbench, the state and key change. Why are there two different states and keys? Does it mean that there are two messages?
Also, the output of the testbench produces 6 different outputs. Which one is the cypher text? Why are there more than one output?
In the description it says that it can work in different modes, how do you define which mode is operating on?
It also says that the same hardware can be used for decryption, how would the decryption be implemented with the code provided?

Thank you,

Ouput length

The documentation does not describe much the waveforms.

Please add some waveforms to describe setup, behaviour and expected results.

add some waveforms to describe behaviour

Aes_256 (and possibly the others) make use of name "out" as port name of the encrypted data bus coming out the verilog module.

The name "out" is a reserved keywork in VHDL so when you put an instance of the verilog core inside a VDHL top you get the below error.
near "out": (vcom-1576) expecting IDENTIFIER.  

To fix the bug is that easy to rename out to something else like dout. 
Thanks

out is a reserved keywork for VHDL

Hello Sir:
     In module one_round of round.v ,the sequence of the member of the last four assign may be wrong. I got a different turn due to the AES.
     In module table_lookup of table.v, the member of t0,t1,t2,t3 may be wrong too.
     I just found these so far.please check it .I cannot upload my picture,sorry for that.

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AES