Turbo Decoder
Syntax Error in VHDL file #9
Open manikanadan opened this issue over 10 years ago
manikanadan commented over 10 years ago
file name: trellis1_synth.vhd ERROR: type conversion std_logic_vector is not allowed as a prefix for an slice name
Description:
This error is raised while checking for syntax errors in trellis1_synth.vhd and the whole project file turoDec.vhd file.
vakaspr009 commented about 10 years ago
how to get rid of this bug ??
ERROR: type conversion std_logic_vector is not allowed as a prefix for an slice name
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