dbrochart

Turbo Decoder

file name: trellis1_synth.vhd
ERROR: type conversion std_logic_vector is not allowed as a prefix for an slice name

Description: 

This error is raised while checking for syntax errors in trellis1_synth.vhd and the whole project file turoDec.vhd file.

Syntax Error in VHDL file

A wishbone interface is needed for setting the coding rate, number of iterations, etc.

Wishbone interface

For this feature, a pseudo-random number generator is needed in the coder and in the decoder, as well as a synchronization mechanism (which is needed anyway - see "Coder/decoder synchronization" request).

In-operation BER monitoring

A synchronization between the coder and the decoder is needed for the puncturing mechanism, the interleavers, and the permuters.

Coder/decoder synchronization

A puncturing mechanism has to be implemented, for higher rates.

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Turbo Decoder