TV80

Instruction DJNZ fails like this:

ADDR Instruction

00E6 ld bc,$0000 00E9 djnz $00E9 00EB di 00EC dec c 00ED jr nz,$00E9

TV80 does not loop around 00E9 but just continues on to 00EB.

I simulated this with iVerilog. I can provide waveforms if you contact me.

Thanks.

I set up the same simulation with Verilator and it ran correctly. Still, there might be something not very standard-ish in the verilog code if two verilog simulators produce different results.

I was wrong: it fails with Verilator too. It seems that the problem is related to the use of a clock enable. DJNZ runs correctly if the input "cen" is set to 1'b1, and fails if the input is a clock enable signal, that effectively halves the clock rate. The clock enable toggles on the negative edge of the original clock.

So this is a genuine bug.

The problem is in file tv80s.v, the tstate always block is not gated by the cen signal, so the tstate advances even when clock enable is low.

To solve it just add a "if (cen)" in that block. Exactly, make line 107:

  else if(cen)

instead of

  else

and that solves the problem.

Sorry for late reply but you have already tracked down the source of the bug. This repository is no longer maintained, the maintained version is now on github: https://github.com/hutch31/tv80

In the github version of the code cen is tied to 1 in tv80s (I have never used clock enable in any of my implementations).