OpenCores

Details

Name: tv80
Created: May 14, 2004
Updated: Jan 30, 2019
SVN Updated: Feb 2, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 10 reported / 8 solved
Star2you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Mature
Additional info:ASIC proven, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

Description

The TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core.

Features

- executes 8080/Z80 instruction set
- cycle timing is similar to original Z80
- small die area
- sample peripheral with GMII interface
- Optional Wishbone wrapper for TV80 core now available

Status

- taped out in TSMC 130nm (250 Mhz, ~20k gates)
- taped out in TSMC 65nm process (125 Mhz)
- Microprocessor-controlled verification environment