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Public Profile of M. Harte, Howard

Info

Username	hharte
Fullname	M. Harte, Howard
Email	hharte@openco... (@opencores.org)
State	California
Country	United States

Projects 5

TV80 7
Z80-Based Vector Graphic Single-Board Computer 1
Wishbone FLASH Interface for Parallel FLASH 4
Wishbone LPC Host and Peripheral Bridge 5
8051 Slave to Wishbone Master Interface 1
Total 18 received

Submitted bugs 6

Open 1

Open Wishbone High Performance Z80 — Core fails some tests using the EXZ80 instruction set exerciser

Closed 5

Closed Wishbone LPC Host and Peripheral Bridge — Serirq: incorrect stop frame

Closed Wishbone LPC Host and Peripheral Bridge — LPC firmware writes must not insert wait-states.

Closed Wishbone LPC Host and Peripheral Bridge — propagate Wishbone errors across LPC interface

Closed Wishbone LPC Host and Peripheral Bridge — LPC DMA does not report READY+MORE for multi-byte transfers

Closed Wishbone LPC Host and Peripheral Bridge — Spec violation for multi-byte firmware accesses

Forum posts 1

1 posts in 1 forum

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