Wishbone FLASH Interface for Parallel FLASH
Project maintainers
Details
Name: wb_flash
Created: Jun 3, 2008
Updated: May 19, 2016
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Jun 3, 2008
Updated: May 19, 2016
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star4you like it: star it!
Other project properties
Category:Memory core
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Wishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E Starter Kit. Provides an 8-bit data interface to the FLASH, and a 32-bit Wishbone Slave Interface with byte enables.
The StrataFlash on the S3E Starter Kit can be programmed using the PicoBlaze RS-232 StrataFlash™ Programmer downloadable from the following site:
http://www.xilinx.com/products/boards/s3estarterreference_designs.htm
Features
- Compatible with Intel StrataFlash J3 on Xilinx Spartan 3E Starter Kit
- Supports byte-mode operation.
- 32-bit Wishbone Slave Interface
Status
- Tested on Xilinx Spartan 3E Starter Kit
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