comparing to T80 vhdl design, I found this is a mismatch

Change committed, will verify correctness tomorrow and close.  Thanks for the report.

Hutchison, Guy

M. Harte, Howard

TV80

in tv80_core.v line 1242,
 original: Pre_XY_F_M<=#1 mcycle;
 should be Pre_XY_F_M <=#1 (mcycle[0])? 1:
                           (mcycle[1])? 2:  
                           (mcycle[2])? 3: 
                           (mcycle[3])? 4:
                           (mcycle[4])? 5:
                           (mcycle[5])? 6:7;

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TV80