TV80

Hi,

First forgive me for disturbing you, i am new to FPGA so i may be using the wrong files from the download, files i used are from tv80_latest(1).tar.gz\tv80\trunk\rtl\core*.* i presummed these are the most recent files. So i used the Z80 core to develope a ZX81 clone on FPGA, the ZX81 usws some tricks to generate the display and relies on exact cycle timing... I found after looking elsewhere that the RET instruction appears to be taking 11 clock cycles instead of 10 as it should. I corrected this behaviour by making a single change to tv80_mcode.v

on line 1483 from TStates = 3'b101; changed to TStates = 3'b100;

I hoe this is useful for you.

Regards Andy Rea

Proposed fix appears to be correct and matches Z80 cycle description of 4/3/3. Let me write a test to check RET behavior after the fix.

Code updated in Github repository <a href="https://github.com/hutch31/tv80">here</a>.

Will update Opencores branch as time permits.