UART 16550 core

All of these apply to module uart_receiver.v

1. I agree completely with ehliar, input signal srx_pad_i absolutely must be registered with the UART clock (clk) to synchronise to the clock domain. Without the sync register (or two), the stability of the state machine in uart_receiver.v is gravely compromised. Suggest two stages of register, and only the final delay stage should be used anywhere else in the design.

2. reg rbit_in is unused, should be deleted.

3. in state machine code, there is an ambiguity in the coding. Note the sr_rec_prepare state section, starting at line 313, where the counter rcounter16 is initialised to 4'b1110 (line 323). Outside the IF-ELSE statement is another assignment for the same counter: rcounter16 <= #1 rcounter16_minus_1; (line 328). This second assignment should be placed inside the ELSE statment.

Original code snippet sr_rec_prepare:begin case (lcr/`UART_LC_BITS/1:0) // number of bits in a word 2'b00 : rbit_counter <= #1 3'b100; 2'b01 : rbit_counter <= #1 3'b101; 2'b10 : rbit_counter <= #1 3'b110; 2'b11 : rbit_counter <= #1 3'b111; endcase if (rcounter16_eq_0) begin rstate <= #1 sr_rec_bit; rcounter16 <= #1 4'b1110; rshift <= #1 0; end else rstate <= #1 sr_rec_prepare; rcounter16 <= #1 rcounter16_minus_1; end

Revised code snippet sr_rec_prepare:begin case (lcr/`UART_LC_BITS/1:0) // number of bits in a word 2'b00 : rbit_counter <= #1 3'b100; 2'b01 : rbit_counter <= #1 3'b101; 2'b10 : rbit_counter <= #1 3'b110; 2'b11 : rbit_counter <= #1 3'b111; endcase if (rcounter16_eq_0) begin rstate <= #1 sr_rec_bit; rcounter16 <= #1 4'b1110; rshift <= #1 0; end else begin // added rstate <= #1 sr_rec_prepare; rcounter16 <= #1 rcounter16_minus_1; // moved inside the IF-ELSE lines end // added end