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UART 16550 core
Overview
News
Downloads
Bugtracker
Open
13
Closed
1
All
14
New issue
Xilinx iSim generates "out of valid range" error
Bug
#14 opened almost 14 years by c.noble
suggested receiver core fixes
Bug
#13 opened over 14 years by eteam
Fatal bug in uart_receiver.v: srx_pad_i is not synchronized at all
Bug
#12 opened over 15 years by ehliar
Problem with 16550 UART core
Bug
#11 opened about 16 years by valentina.lomi
TERI in Modem Status Register Not To Specification
Bug
#10 opened over 17 years by vchan
Does uart_int.v testcase run successfully?
Bug
#9 opened almost 18 years by ocghost
about rs
Request
#8 opened over 18 years by ocghost
Need to fix commenting-out style in rtl/verilog/uart_defines.v
Bug
#7 opened over 18 years by ocghost
Need to fix commenting-out style in rtl/verilog/uart_defines.v
Bug
#6 opened over 18 years by ocghost
student
Bug
#5 opened about 19 years by paul_cooke_98
VHDL Implementation
Request
#4 opened over 19 years by ocghost
Typo in documentation
Bug
#3 opened over 19 years by ocghost
Three bugs
Bug
#2 opened almost 20 years by ocghost
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