UART 16550 core

Codes at uart_regs.v 1. Changes tf_push to combinational logic 2. Changes msrUART_MS_CDCD:UART_MS_CCTS value from {dcd_c, ri_c, dsr_c, cts_c} to {~dcd_c, ~ri_c, ~dsr_c, ~cts_c} 3. Change modem outputs value from assign rts_n = mcr`UART_MC_RTS; assign dtr_n = mcr`UART_MC_DTR; To : assign rts_n = ~mcr`UART_MC_RTS; assign dtr_n = ~mcr`UART_MC_DTR;

The tf_push thing is quite a problem. This is because the fifo latches in the data the clock cycle after the write enable. If your write data remains valid for one more clock cycle then there is no problem, if the write data changes after the write enable (As in my case) you will get garbage written to the transmit fifo. As chenxj suggested changing the tf_push to combinational so it is valid one clock cycle earlier will fix the problem.

I agree with items 2 & 3. Rev. 0.6 of the specification call out the modem inputs and outputs to be inverted. I also tested my 16550 DUART in my ASCI and they are also inverted.

I too have confirmed in hardware that 2 & 3 are definite bugs.