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Need to fix commenting-out style in rtl/verilog/uart_defines.v #7
Open ocghost opened this issue almost 18 years ago
ocghost commented almost 18 years ago

Hi. There are numerous instances in rtl/verilog/uart_defines.v of using single line comments ("//") in a `define statement. For me (at least), the Modelsim simulator barfs with this.

For example, if you define TRUE 1 // Hi mom in a header file and then later oninclude that header file and try to assign something the macro TRUE: foo <= `TRUE; with a simplistic substitution, you would get foo <= 1 // Hi mom; which is a syntax error (missing semicolon).

This is why you should define `define TRUE 1 / Hi mom using no single line comments! /

Some C compilers have the same issue. This is why you should not use single line comments on a `define or #define macro assignment!

Here is my proposed patch to rtl/verilog/uart_defines.v. This is the output of diff -c3 (your version) (my patched version).

Regards, Jeff

*** dist/uart_defines.v Fri Sep 12 00:26:58 2003 --- uart_defines.v Mon May 15 10:53:55 2006


* 152,234 **

// `define UART_HAS_BAUDRATE_OUTPUT

! // Register addresses ! define UART_REG_RBUART_ADDR_WIDTH'd0 // receiver buffer ! define UART_REG_TRUART_ADDR_WIDTH'd0 // transmitter ! define UART_REG_IEUART_ADDR_WIDTH'd1 // Interrupt enable ! define UART_REG_IIUART_ADDR_WIDTH'd2 // Interrupt identification ! define UART_REG_FCUART_ADDR_WIDTH'd2 // FIFO control ! define UART_REG_LCUART_ADDR_WIDTH'd3 // Line Control ! define UART_REG_MCUART_ADDR_WIDTH'd4 // Modem control ! define UART_REG_LSUART_ADDR_WIDTH'd5 // Line status ! define UART_REG_MSUART_ADDR_WIDTH'd6 // Modem status ! define UART_REG_SRUART_ADDR_WIDTH'd7 // Scratch register ! define UART_REG_DL1UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) define UART_REG_DL2UART_ADDR_WIDTH'd1

! // Interrupt Enable register bits ! define UART_IE_RDA 0 // Received Data available interrupt !define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt ! define UART_IE_RLS 2 // Receiver Line Status Interrupt !define UART_IE_MS 3 // Modem Status Interrupt ! ! // Interrupt Identification register bits ! define UART_II_IP 0 // Interrupt pending when 0 !define UART_II_II 3:1 // Interrupt identification ! ! // Interrupt identification values for bits 3:1 ! define UART_II_RLS 3'b011 // Receiver Line Status !define UART_II_RDA 3'b010 // Receiver Data available ! define UART_II_TI 3'b110 // Timeout Indication !define UART_II_THRE 3'b001 // Transmitter Holding Register empty ! define UART_II_MS 3'b000 // Modem Status ! ! // FIFO Control Register bits !define UART_FC_TL 1:0 // Trigger level ! ! // FIFO trigger level values ! define UART_FC_1 2'b00 !define UART_FC_4 2'b01 define UART_FC_8 2'b10define UART_FC_14 2'b11

! // Line Control register bits ! define UART_LC_BITS 1:0 // bits in character !define UART_LC_SB 2 // stop bits ! define UART_LC_PE 3 // parity enable !define UART_LC_EP 4 // even parity ! define UART_LC_SP 5 // stick parity !define UART_LC_BC 6 // Break control ! `define UART_LC_DL 7 // Divisor Latch access bit

! // Modem Control register bits define UART_MC_DTR 0define UART_MC_RTS 1 define UART_MC_OUT1 2define UART_MC_OUT2 3 ! `define UART_MC_LB 4 // Loopback mode

! // Line Status Register bits ! define UART_LS_DR 0 // Data ready !define UART_LS_OE 1 // Overrun Error ! define UART_LS_PE 2 // Parity Error !define UART_LS_FE 3 // Framing Error ! define UART_LS_BI 4 // Break interrupt !define UART_LS_TFE 5 // Transmit FIFO is empty ! define UART_LS_TE 6 // Transmitter Empty indicator !define UART_LS_EI 7 // Error indicator

! // Modem Status Register bits ! define UART_MS_DCTS 0 // Delta signalsdefine UART_MS_DDSR 1 define UART_MS_TERI 2define UART_MS_DDCD 3 ! define UART_MS_CCTS 4 // Complement signalsdefine UART_MS_CDSR 5 define UART_MS_CRI 6define UART_MS_CDCD 7

! // FIFO parameter defines

define UART_FIFO_WIDTH 8define UART_FIFO_DEPTH 16 --- 152,234 ----

// `define UART_HAS_BAUDRATE_OUTPUT

! / Register addresses / ! define UART_REG_RBUART_ADDR_WIDTH'd0 / receiver buffer / ! define UART_REG_TRUART_ADDR_WIDTH'd0 / transmitter / ! define UART_REG_IEUART_ADDR_WIDTH'd1 / Interrupt enable / ! define UART_REG_IIUART_ADDR_WIDTH'd2 / Interrupt identification / ! define UART_REG_FCUART_ADDR_WIDTH'd2 / FIFO control / ! define UART_REG_LCUART_ADDR_WIDTH'd3 / Line Control / ! define UART_REG_MCUART_ADDR_WIDTH'd4 / Modem control / ! define UART_REG_LSUART_ADDR_WIDTH'd5 / Line status / ! define UART_REG_MSUART_ADDR_WIDTH'd6 / Modem status / ! define UART_REG_SRUART_ADDR_WIDTH'd7 / Scratch register / ! define UART_REG_DL1UART_ADDR_WIDTH'd0 / Divisor latch bytes (1-2) / define UART_REG_DL2UART_ADDR_WIDTH'd1

! / Interrupt Enable register bits / ! define UART_IE_RDA 0 /* Received Data available interrupt */ !define UART_IE_THRE 1 / Transmitter Holding Register empty interrupt / ! define UART_IE_RLS 2 /* Receiver Line Status Interrupt */ !define UART_IE_MS 3 / Modem Status Interrupt / ! ! / Interrupt Identification register bits / ! define UART_II_IP 0 /* Interrupt pending when 0 */ !define UART_II_II 3:1 / Interrupt identification / ! ! / Interrupt identification values for bits 3:1 / ! define UART_II_RLS 3'b011 /* Receiver Line Status */ !define UART_II_RDA 3'b010 / Receiver Data available / ! define UART_II_TI 3'b110 /* Timeout Indication */ !define UART_II_THRE 3'b001 / Transmitter Holding Register empty / ! define UART_II_MS 3'b000 /* Modem Status */ ! ! /* FIFO Control Register bits */ !define UART_FC_TL 1:0 / Trigger level / ! ! / FIFO trigger level values / ! define UART_FC_1 2'b00 */ !define UART_FC_4 2'b01 */ define UART_FC_8 2'b10define UART_FC_14 2'b11

! / Line Control register bits / ! define UART_LC_BITS 1:0 /* bits in character */ !define UART_LC_SB 2 / stop bits / ! define UART_LC_PE 3 /* parity enable */ !define UART_LC_EP 4 / even parity / ! define UART_LC_SP 5 /* stick parity */ !define UART_LC_BC 6 / Break control / ! `define UART_LC_DL 7 / Divisor Latch access bit /

! / Modem Control register bits / define UART_MC_DTR 0define UART_MC_RTS 1 define UART_MC_OUT1 2define UART_MC_OUT2 3 ! `define UART_MC_LB 4 / Loopback mode /

! / Line Status Register bits / ! define UART_LS_DR 0 /* Data ready */ !define UART_LS_OE 1 / Overrun Error / ! define UART_LS_PE 2 /* Parity Error */ !define UART_LS_FE 3 / Framing Error / ! define UART_LS_BI 4 /* Break interrupt */ !define UART_LS_TFE 5 / Transmit FIFO is empty / ! define UART_LS_TE 6 /* Transmitter Empty indicator */ !define UART_LS_EI 7 / Error indicator /

! / Modem Status Register bits / ! define UART_MS_DCTS 0 /* Delta signals */define UART_MS_DDSR 1 define UART_MS_TERI 2define UART_MS_DDCD 3 ! define UART_MS_CCTS 4 /* Complement signals */define UART_MS_CDSR 5 define UART_MS_CRI 6define UART_MS_CDCD 7

! / FIFO parameter defines /

define UART_FIFO_WIDTH 8define UART_FIFO_DEPTH 16


* 238,246 ** `define UART_FIFO_REC_WIDTH 11

! define VERBOSE_WB 0 // All activity on the WISHBONE is recorded !define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) ! `define FAST_TEST 1 // 64/1024 packets are sent

--- 238,246 ---- `define UART_FIFO_REC_WIDTH 11

! define VERBOSE_WB 0 /* All activity on the WISHBONE is recorded */ !define VERBOSE_LINE_STATUS 0 / Details about the lsr (line status register) / ! `define FAST_TEST 1 / 64/1024 packets are sent /

ocghost commented almost 18 years ago

Sorry. Hit refresh on browser and it re-submitted my request. Pls delete this duplicate request.

ocghost commented almost 17 years ago

hai , This is very use for me. I need full code which ar e designed in Verilog.

regard Thiru

ocghost commented almost 17 years ago

hai , This is very use for me. I need full code which ar e designed in Verilog.

regard Thiru


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