Mohor, Igor

Markovic, Tadej

UART 16550 core

The VHDL 16550 UART generates an error using Xilinx iSim (I’m using 12.3 M.70d). Ther error is:
ERROR: Value -2147483648 is out of valid range : 0 TO 8

This is caused by line 29 of gh_uart_Rx_8bit.vhd, which reads:
                                                num_bits  : in integer;
I think that this should read
                                                num_bits  : in integer:=8;

Charlie

Xilinx iSim generates "out of valid range" error

All of these apply to module uart_receiver.v

1.  I agree completely with ehliar, input signal srx_pad_i absolutely must be registered with the UART clock (clk) to synchronise to the clock domain.  Without the sync register (or two), the stability of the state machine in uart_receiver.v is gravely compromised.  Suggest two stages of register, and only the final delay stage should be used anywhere else in the design.

2.  reg rbit_in is unused, should be deleted.

3.  in state machine code, there is an ambiguity in the coding.  Note the [sr_rec_prepare] state section, starting at line 313, where the counter rcounter16 is initialised to 4'b1110 (line 323).  Outside the IF-ELSE statement is another assignment for the same counter: [rcounter16 <= #1 rcounter16_minus_1;] (line 328).  This second assignment should be placed inside the ELSE statment.


Original code snippet
sr_rec_prepare:begin
	case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
	2'b00 : rbit_counter <= #1 3'b100;
	2'b01 : rbit_counter <= #1 3'b101;
	2'b10 : rbit_counter <= #1 3'b110;
	2'b11 : rbit_counter <= #1 3'b111;
	endcase
	if (rcounter16_eq_0)
	begin
		rstate		<= #1 sr_rec_bit;
		rcounter16	<= #1 4'b1110;
		rshift		<= #1 0;
	end
	else
		rstate <= #1 sr_rec_prepare;
	rcounter16 <= #1 rcounter16_minus_1;
end

Revised code snippet
sr_rec_prepare:begin
	case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
	2'b00 : rbit_counter <= #1 3'b100;
	2'b01 : rbit_counter <= #1 3'b101;
	2'b10 : rbit_counter <= #1 3'b110;
	2'b11 : rbit_counter <= #1 3'b111;
	endcase
	if (rcounter16_eq_0)
	begin
		rstate		<= #1 sr_rec_bit;
		rcounter16	<= #1 4'b1110;
		rshift		<= #1 0;
	end
	else
	begin	// added
		rstate <= #1 sr_rec_prepare;
		rcounter16 <= #1 rcounter16_minus_1; // moved inside the IF-ELSE lines
	end	// added
end

suggested receiver core fixes

srx_pad_i is not synchronized to the clock domain of the UART in uart_receiver.v.

Without synchronization I'm not able to use the UART for anything but text entry. With synchronization change I can easily download a 6 megabyte text file over the UART without any problems.

Fatal bug in uart_receiver.v: srx_pad_i is not synchronized at all

Hallo,
I'm not sure I found a bug but I used the core and I found a problem. I'm using 9600 baudrate with fifo trigger level set to 1 and no dma.
Transmission goes perfectly but reception has the following strange behaviour: if I send to the UART the letter A, it receives another character (0). If, after letter A I send the letter B, it still receives 0. Only after 15 transmissions of characters, the UART actually receives letter A, and following another transmission of a character, it receives the letter B and so on.
It seems that there is a delay of 15 characters that I can't remove.
I've tried to reset the FIFO during initialization of the UART and tried to flush it but without any result. Can anyone help me?

Thank you 
Valentina

Problem with 16550 UART core

According to the Rev. 0.6 Specification,  that bit is supposed to be set only when going from low to high state.  However,  the code is treating it same as the other three Delta indicator bits.  The specification is correct.  Need to change the code such that TERI bit is set only when delayed_modem_signal[2] and ~ri.

TERI in Modem Status Register Not To Specification

I tried to run the supplied testcase, "uart_int.v", but it fails in ModelSim.  The message in uart_interrupts_verbose.log is shown below:

Time: 5734521200    (testbench.tx_fifo_status_changing)
*E, Bit 5 of LSR register not '1'!

I just wanted to verify that someone has successfully run the testcase before I spend any more time troubleshooting it.

Regards,
Dalton

Does uart_int.v testcase run successfully?

I want to know about rs code,would like you to give me some
  vhdl code abuout rs?
Thank you !!

about  rs

Hi.  There are numerous instances in rtl/verilog/uart_defines.v of using single line comments ("//") in a `define statement.  For me (at least), the Modelsim simulator barfs with this.

For example, if you 
`define TRUE 1 // Hi mom
in a header file and then later on `include that header file and
try to assign something the macro TRUE:
foo <= `TRUE;
with a simplistic substitution, you would get
foo <= 1 // Hi mom;
which is a syntax error (missing semicolon).

This is why you should define
`define TRUE 1 /* Hi mom using no single line comments! */

Some C compilers have the same issue.  This is why you should not use single line comments on a `define or #define macro assignment!

Here is my proposed patch to rtl/verilog/uart_defines.v.  This is the output of diff -c3 (your version) (my patched version).

Regards,
Jeff

*** dist/uart_defines.v	Fri Sep 12 00:26:58 2003
--- uart_defines.v	Mon May 15 10:53:55 2006
***************
*** 152,234 ****
  
  // `define UART_HAS_BAUDRATE_OUTPUT
  
! // Register addresses
! `define UART_REG_RB	`UART_ADDR_WIDTH'd0	// receiver buffer
! `define UART_REG_TR  `UART_ADDR_WIDTH'd0	// transmitter
! `define UART_REG_IE	`UART_ADDR_WIDTH'd1	// Interrupt enable
! `define UART_REG_II  `UART_ADDR_WIDTH'd2	// Interrupt identification
! `define UART_REG_FC  `UART_ADDR_WIDTH'd2	// FIFO control
! `define UART_REG_LC	`UART_ADDR_WIDTH'd3	// Line Control
! `define UART_REG_MC	`UART_ADDR_WIDTH'd4	// Modem control
! `define UART_REG_LS  `UART_ADDR_WIDTH'd5	// Line status
! `define UART_REG_MS  `UART_ADDR_WIDTH'd6	// Modem status
! `define UART_REG_SR  `UART_ADDR_WIDTH'd7	// Scratch register
! `define UART_REG_DL1	`UART_ADDR_WIDTH'd0	// Divisor latch bytes (1-2)
  `define UART_REG_DL2	`UART_ADDR_WIDTH'd1
  
! // Interrupt Enable register bits
! `define UART_IE_RDA	0	// Received Data available interrupt
! `define UART_IE_THRE	1	// Transmitter Holding Register empty interrupt
! `define UART_IE_RLS	2	// Receiver Line Status Interrupt
! `define UART_IE_MS	3	// Modem Status Interrupt
! 
! // Interrupt Identification register bits
! `define UART_II_IP	0	// Interrupt pending when 0
! `define UART_II_II	3:1	// Interrupt identification
! 
! // Interrupt identification values for bits 3:1
! `define UART_II_RLS	3'b011	// Receiver Line Status
! `define UART_II_RDA	3'b010	// Receiver Data available
! `define UART_II_TI	3'b110	// Timeout Indication
! `define UART_II_THRE	3'b001	// Transmitter Holding Register empty
! `define UART_II_MS	3'b000	// Modem Status
! 
! // FIFO Control Register bits
! `define UART_FC_TL	1:0	// Trigger level
! 
! // FIFO trigger level values
! `define UART_FC_1		2'b00
! `define UART_FC_4		2'b01
  `define UART_FC_8		2'b10
  `define UART_FC_14	2'b11
  
! // Line Control register bits
! `define UART_LC_BITS	1:0	// bits in character
! `define UART_LC_SB	2	// stop bits
! `define UART_LC_PE	3	// parity enable
! `define UART_LC_EP	4	// even parity
! `define UART_LC_SP	5	// stick parity
! `define UART_LC_BC	6	// Break control
! `define UART_LC_DL	7	// Divisor Latch access bit
  
! // Modem Control register bits
  `define UART_MC_DTR	0
  `define UART_MC_RTS	1
  `define UART_MC_OUT1	2
  `define UART_MC_OUT2	3
! `define UART_MC_LB	4	// Loopback mode
  
! // Line Status Register bits
! `define UART_LS_DR	0	// Data ready
! `define UART_LS_OE	1	// Overrun Error
! `define UART_LS_PE	2	// Parity Error
! `define UART_LS_FE	3	// Framing Error
! `define UART_LS_BI	4	// Break interrupt
! `define UART_LS_TFE	5	// Transmit FIFO is empty
! `define UART_LS_TE	6	// Transmitter Empty indicator
! `define UART_LS_EI	7	// Error indicator
  
! // Modem Status Register bits
! `define UART_MS_DCTS	0	// Delta signals
  `define UART_MS_DDSR	1
  `define UART_MS_TERI	2
  `define UART_MS_DDCD	3
! `define UART_MS_CCTS	4	// Complement signals
  `define UART_MS_CDSR	5
  `define UART_MS_CRI	6
  `define UART_MS_CDCD	7
  
! // FIFO parameter defines
  
  `define UART_FIFO_WIDTH	8
  `define UART_FIFO_DEPTH	16
--- 152,234 ----
  
  // `define UART_HAS_BAUDRATE_OUTPUT
  
! /* Register addresses */
! `define UART_REG_RB	`UART_ADDR_WIDTH'd0	/* receiver buffer */
! `define UART_REG_TR  `UART_ADDR_WIDTH'd0	/* transmitter */
! `define UART_REG_IE	`UART_ADDR_WIDTH'd1	/* Interrupt enable */
! `define UART_REG_II  `UART_ADDR_WIDTH'd2	/* Interrupt identification */
! `define UART_REG_FC  `UART_ADDR_WIDTH'd2	/* FIFO control */
! `define UART_REG_LC	`UART_ADDR_WIDTH'd3	/* Line Control */
! `define UART_REG_MC	`UART_ADDR_WIDTH'd4	/* Modem control */
! `define UART_REG_LS  `UART_ADDR_WIDTH'd5	/* Line status */
! `define UART_REG_MS  `UART_ADDR_WIDTH'd6	/* Modem status */
! `define UART_REG_SR  `UART_ADDR_WIDTH'd7	/* Scratch register */
! `define UART_REG_DL1	`UART_ADDR_WIDTH'd0	/* Divisor latch bytes (1-2) */
  `define UART_REG_DL2	`UART_ADDR_WIDTH'd1
  
! /* Interrupt Enable register bits */
! `define UART_IE_RDA	0	/* Received Data available interrupt */
! `define UART_IE_THRE	1	/* Transmitter Holding Register empty interrupt */
! `define UART_IE_RLS	2	/* Receiver Line Status Interrupt */
! `define UART_IE_MS	3	/* Modem Status Interrupt */
! 
! /* Interrupt Identification register bits */
! `define UART_II_IP	0	/* Interrupt pending when 0 */
! `define UART_II_II	3:1	/* Interrupt identification */
! 
! /* Interrupt identification values for bits 3:1 */
! `define UART_II_RLS	3'b011	/* Receiver Line Status */
! `define UART_II_RDA	3'b010	/* Receiver Data available */
! `define UART_II_TI	3'b110	/* Timeout Indication */
! `define UART_II_THRE	3'b001	/* Transmitter Holding Register empty */
! `define UART_II_MS	3'b000	/* Modem Status */
! 
! /* FIFO Control Register bits */
! `define UART_FC_TL	1:0	/* Trigger level */
! 
! /* FIFO trigger level values */
! `define UART_FC_1		2'b00 */
! `define UART_FC_4		2'b01 */
  `define UART_FC_8		2'b10
  `define UART_FC_14	2'b11
  
! /* Line Control register bits */
! `define UART_LC_BITS	1:0	/* bits in character */
! `define UART_LC_SB	2	/* stop bits */
! `define UART_LC_PE	3	/* parity enable */
! `define UART_LC_EP	4	/* even parity */
! `define UART_LC_SP	5	/* stick parity */
! `define UART_LC_BC	6	/* Break control */
! `define UART_LC_DL	7	/* Divisor Latch access bit */
  
! /* Modem Control register bits */
  `define UART_MC_DTR	0
  `define UART_MC_RTS	1
  `define UART_MC_OUT1	2
  `define UART_MC_OUT2	3
! `define UART_MC_LB	4	/* Loopback mode */
  
! /* Line Status Register bits */
! `define UART_LS_DR	0	/* Data ready */
! `define UART_LS_OE	1	/* Overrun Error */
! `define UART_LS_PE	2	/* Parity Error */
! `define UART_LS_FE	3	/* Framing Error */
! `define UART_LS_BI	4	/* Break interrupt */
! `define UART_LS_TFE	5	/* Transmit FIFO is empty */
! `define UART_LS_TE	6	/* Transmitter Empty indicator */
! `define UART_LS_EI	7	/* Error indicator */
  
! /* Modem Status Register bits */
! `define UART_MS_DCTS	0	/* Delta signals */
  `define UART_MS_DDSR	1
  `define UART_MS_TERI	2
  `define UART_MS_DDCD	3
! `define UART_MS_CCTS	4	/* Complement signals */
  `define UART_MS_CDSR	5
  `define UART_MS_CRI	6
  `define UART_MS_CDCD	7
  
! /* FIFO parameter defines */
  
  `define UART_FIFO_WIDTH	8
  `define UART_FIFO_DEPTH	16
***************
*** 238,246 ****
  `define UART_FIFO_REC_WIDTH  11
  
  
! `define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
! `define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
! `define FAST_TEST   1           // 64/1024 packets are sent
  
  
  
--- 238,246 ----
  `define UART_FIFO_REC_WIDTH  11
  
  
! `define VERBOSE_WB  0           /* All activity on the WISHBONE is recorded */
! `define VERBOSE_LINE_STATUS 0   /* Details about the lsr (line status register) */
! `define FAST_TEST   1           /* 64/1024 packets are sent */

Need to fix commenting-out style in rtl/verilog/uart_defines.v

MCR register is not readable from address `UART_REG_MC.

The following fix :
    
		`UART_REG_MS	: wb_dat_o = msr;
		`UART_REG_SR	: wb_dat_o = scratch;
	   	default:  wb_dat_o = 8'b0; // ??
	endcase // case(wb_addr_i)

changed to :

		`UART_REG_MS	: wb_dat_o = msr;
		`UART_REG_SR	: wb_dat_o = scratch;
	        `UART_REG_MC    : wb_dat_o = {4'b000, mcr };	  
		default:  wb_dat_o = 8'b0; // ??
	endcase // case(wb_addr_i)

student

Dear all,

Does anyone have the VHDL Implementation of UART16550?

Thanks and Regards,
Jagan J

VHDL Implementation

file: UART_spec.pdf
On Page 7 clocks table:
Rates max: 1258 MHz for 1200bps ?
seems not to be correct

Typo in documentation

Codes at uart_regs.v
 1. Changes tf_push to combinational logic
 2. Changes msr[`UART_MS_CDCD:`UART_MS_CCTS] value from {dcd_c, ri_c, dsr_c, cts_c} to {~dcd_c, ~ri_c, ~dsr_c, ~cts_c}
3. Change modem outputs value from
	assign rts_n = mcr[`UART_MC_RTS];
	assign dtr_n = mcr[`UART_MC_DTR];
   To :
	assign rts_n = ~mcr[`UART_MC_RTS];
	assign dtr_n = ~mcr[`UART_MC_DTR];

Three bugs

I am using the UART core in 32-bit configuration (BIG ENDIAN).
The UART does not respond correctly to the SEL_I signal.

The simplest case to exhibit the problem is as follows (all wishbone transactions):

reset UART
read from Receive buffer  \w SEL_I = 4'b0001
                                       wb_adr_i = 32'h00000000

I expect wb_dat_o[7:0] = 8'hxx 
 but get wb_dat_o[7:0] = 8'h00

But if I set 
SEL_I = 4'b1000 
wb_dat_o[31:24] =8'hxx
as expected.

for the case SEL_I = 4'b0001
wb_interface sends
wb_adr_int = 8'h03
to regs

The following code will not select the correct output

// Asynchronous reading here because the outputs are sampled in uart_wb.v file 
always @(dl or dlab or ier or iir or scratch
			or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i)   // asynchrounous reading
begin
	case (wb_addr_i)
		`UART_REG_RB   : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
		`UART_REG_IE	: wb_dat_o = dlab ? dl[`UART_DL2] : ier;
		`UART_REG_II	: wb_dat_o = {4'b1100,iir};
		`UART_REG_LC	: wb_dat_o = lcr;
		`UART_REG_LS	: wb_dat_o = lsr;
		`UART_REG_MS	: wb_dat_o = msr;
		`UART_REG_SR	: wb_dat_o = scratch;
		default:  wb_dat_o = 8'b0; // ??
	endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...


I would expect 

`UART_REG_RB   : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];

to execute but since wb_addr_i = 8'h03 it will not execute.


Answer:
First of all let me tell you, that the UART16550 is used in 32-bit BIGENDIAN mode
in our system and it works without any problems.
Now let's go to the problem. You didn't understand the functionality of the UART16650 core.
If you make a 32-bit big_endian read to the address 0x0 and use select = 0x1, this means that
you're reading from the address 0x3 (on the 8-bit bus).

So the address wb_adr_i = 0x0 + wb_sel_i = 0x1 is changed to address wb_adr_int = 0x3,
which is used for reading the data from the registers.

If you have further problems, contact me directly at igor.mohor@gmail.com

Best regards,
      Igor

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UART 16550 core