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Its not in Verilog #1
Closed shaloob opened this issue almost 12 years ago
shaloob commented almost 12 years ago

The code submitted here is in VHDL... But in the language feild its Verilog...

motilito commented almost 12 years ago

This is a very strange bug report. I'm pretty sure that this project code is written in Verilog and not VHDL. It just might be that you intended this bug report for a different project? Moti

motilito closed this almost 12 years ago

No one