UART to Bus
Its not in Verilog #1
Closed shaloob opened this issue over 15 years ago
shaloob commented over 15 years ago
The code submitted here is in VHDL... But in the language feild its Verilog...
motilito commented over 15 years ago
This is a very strange bug report. I'm pretty sure that this project code is written in Verilog and not VHDL. It just might be that you intended this bug report for a different project? Moti
motilito closed this over 15 years ago
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