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* UART to Bus :: News

News
Feb 25, 2012Updated block diagram to include the bus request/grant signals.Litochevski, Moti
Feb 17, 2012Chaged license to BSDLitochevski, Moti
Nov 16, 2011Updated overview pageLitochevski, Moti
Apr 15, 2011Added Lattice synthesys results, many thanks to Paul V. ShatovLitochevski, Moti
Aug 4, 2010Updated project language to Verilog & VHDLLitochevski, Moti
Jul 18, 2010VHDL version now availableMULLER, Steve
Jul 7, 2010VHDL version coming soonMULLER, Steve
Jul 5, 2010Updating core overviewLitochevski, Moti
Jul 5, 2010Updating project overviewLitochevski, Moti
Apr 12, 2010Updated additional info in the project pageLitochevski, Moti
Apr 3, 2010Another try in updating project infoLitochevski, Moti
Apr 3, 2010Updated additional info in the project pageLitochevski, Moti
Apr 2, 2010Corrected problems with the test bench. Updated documentation.Litochevski, Moti
Feb 27, 2010Update project status to done.Litochevski, Moti
Feb 15, 2010Files uploaded to SVN server.Litochevski, Moti
Feb 12, 2010Updated description of project. Coming soon.Litochevski, Moti
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