UART to Bus
News
| Feb 25, 2012 | Updated block diagram to include the bus request/grant signals. | Litochevski, Moti |
| Feb 17, 2012 | Chaged license to BSD | Litochevski, Moti |
| Nov 16, 2011 | Updated overview page | Litochevski, Moti |
| Apr 15, 2011 | Added Lattice synthesys results, many thanks to Paul V. Shatov | Litochevski, Moti |
| Aug 4, 2010 | Updated project language to Verilog & VHDL | Litochevski, Moti |
| Jul 18, 2010 | VHDL version now available | MULLER, Steve |
| Jul 7, 2010 | VHDL version coming soon | MULLER, Steve |
| Jul 5, 2010 | Updating core overview | Litochevski, Moti |
| Jul 5, 2010 | Updating project overview | Litochevski, Moti |
| Apr 12, 2010 | Updated additional info in the project page | Litochevski, Moti |
| Apr 3, 2010 | Another try in updating project info | Litochevski, Moti |
| Apr 3, 2010 | Updated additional info in the project page | Litochevski, Moti |
| Apr 2, 2010 | Corrected problems with the test bench. Updated documentation. | Litochevski, Moti |
| Feb 27, 2010 | Update project status to done. | Litochevski, Moti |
| Feb 15, 2010 | Files uploaded to SVN server. | Litochevski, Moti |
| Feb 12, 2010 | Updated description of project. Coming soon. | Litochevski, Moti |
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