UART to Bus
SDC file #2
Closed quiescent opened this issue about 14 years ago
quiescent commented about 14 years ago
Is there an SDC timing file for this project? I am trying to build this project for an Altera device, and the compiler is requesting an SDC file.
Critical Warning: Synopsys Design Constraints File file not found: 'uart2bus_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
myfingerhurt commented over 13 years ago
It's not a problem.You can generate it in your Timequest.
motilito closed this over 13 years ago
tshirato commented about 7 years ago
Type your text here
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