UART to Bus

Thanks for sharing this core. uart_tasks.v cannot compile by ModelSim.

It produces 3 errors:

Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 ** Error: (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.

** Error: (vlog-2730) Undefined variable: 'serial_out'.

** Error: Verilog Compiler exiting

Can you help or is there any one with same issue? Thanks