UCore
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2006-01-07 05:36 | ucsys-0.0.1.rar | This file is the latest code that I'm developing. The packet contains the ucsys system which is consit of a 32k data_ram ,a 32k inst_rom ,a uart ,a timer ,and clk divider. The ucosII port and the system lies in the ucosii folder. The dhrystone port is in the dhrystone folder, it's score is 140DMIPS when run at 100Mhz. There are synplify and modelsim project file in the folder ,too . You can download the latest stable version from the cvs repository a few days later. |
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