1G eth UDP / IP Stack

For the "Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.4" in the "Local Link Transmitter Interface" the signals are the next:

-- Local link Transmitter Interface - EMAC0 TX_LL_CLOCK_0 : in std_logic; TX_LL_RESET_0 : in std_logic; TX_LL_DATA_0 : in std_logic_vector(7 downto 0); TX_LL_SOF_N_0 : in std_logic; TX_LL_EOF_N_0 : in std_logic; TX_LL_SRC_RDY_N_0 : in std_logic; TX_LL_DST_RDY_N_0 : out std_logic;

In the "UDP_Complete_nomac" in the "MAC Transmitter Interface" the signals are the next:

-- MAC Transmitter mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx mac_tx_tvalid : out std_logic; -- tdata is valid mac_tx_tready : in std_logic; -- mac is ready to accept data mac_tx_tlast : out std_logic; -- indicates last byte of frame

So, he lacks a signal for the first byte of the frame (Start of frame)

Thanks for you project and sorry my bad english !

I have not looked at the V5 emac wrapper v1.4, but I assume that the SOF should be asserted with the first byte being placed on the mac_tx_tdata bus.

Fixed in v1.1