1G eth UDP / IP Stack

Project maintainers

Details

Name: udp_ip_stack
Created: Oct 11, 2011
Updated: Mar 5, 2018
SVN Updated: Apr 30, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 18 reported / 12 solved

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Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

Description

Implements UDP, IPv4, ARP protocols
Zero latency between UDP and MAC layer (combinatorial transfer during user data phase)
Allows full control of UDP src & dst ports on TX.
Provides access to UDP src & dst ports on RX (user filtering)
Couples directly to Xilinx Tri-Mode eth Mac via AXI interface
choice of ARPV2 layer with multislot cache, or smaller single slot ARP for point to point implementations
Separate building blocks to create custom stacks
Easy to tap into the IP layer directly
Separate clock domains for tx & rx paths
Tested for 1Gbit Ethernet, but applicable to 100M and 10M
More detail in doco under Downloads
- provided by Peter Fall and the FIXQRL project
- Applicable license is the "BSD 3-Clause License"