1G eth UDP / IP Stack

hello shekhar here, i want to use your design in one of my application for data transfer between FPGA(ML605) and PC. i tried to implement your design using ISE 13.1,i found that you have used "Xilinx LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v2.1".i am trying to add this IP core in design(.XCO file has not been given) but entity of ethernet mac core looks different as u used in the design.i am not able to port map the signals with IP core. plz send me .XCO file or guide me to proceed.

Added rtl/vhdl/ipcores/xilinx/mac_layer_v2_2.xco to trunk.

Please evaluate and let me know if you have further questions.

Dear thanks for the reply i downloaded the design but it seems this "/ipcores/xilinx/mac_layer_v2_2.xco" folder has not been added,plz confirm

i got the mac_layer_v2_2.xco. i will evaluate and come back to you. thanks.

dear i am using ISE13.1 which support embedded tri mode ethernet wrapper v1.5 and v2.1.it does not support v2.2.so i m not able to synthesize the design with given .XCO file.is there any other way or i have to use some other version of ISE?

Added mac_layer_v2_1.xco - please see the readme.txt file in the same dir.

thanks for reply i am geting this error message while synthesize."required file for mac_layer_v2_1_synth.vhd for the IP core mac_layer_v2_1.xco was not found in the IP core source directory".In order for synthesis to run successfully,you will either need to copy the file(s) to IP core source directory or regenerate the core." i dont have these files so i tried to regenerate the core now i am geting following erroe message. "Started : "Regenerate Core". CoreGen has not been configured with any user repositories. CoreGen has been configured with the following Xilinx repositories:

• 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' [] ERROR: could not find existing IP in project mac_layer_v2_1.cgc. Core Generator regen command failed.

Process "Regenerate Core" failed" is there any prblem with ISE version or some thing else? which version of ISE you r using?i am using ISE13.1.

Hi Chandra,

I am currently on ISE 13.4, although I have used both 13.2 and 13.1 earlier in this development.

You might want to either upgrade to an ISE that contains the v2.2 mac, or generate the core from scratch. I used a very basic core config with 1G only, no management interface, no filtering in the MAC layer.

You could generate from scratch and compare the resultant XCO file with the one I provided to see if you got most of the parameters correct. I think the MAC layer interface did change slightly between 2.1 and 2.2, but you should be able to figure this out. You could either write a small adapter layer between the bottom of the UDP stk and the top of the MAC layer, or make some changes to the example code that generated with the core.

Regarding the coregen errors, I have not seen these errors before, but you might find some help in the xilinx forums.

Regards, Peter

Dear peter as i told you,i am using ISE13.1,i tried to generate IP core MAC_v_2_1.i observed that the 2 important signals GMII_TX_CLK and GMII_RX_CLK are missing in the genetaed .VHD file.i tried to comare this .VHD file with the file supplied by you.i obsered that entity are not matching. i used following options while generating IP core. PHY interface:RGMII Speed:10/100/1000 management interface:none address filter:NO this is the entity of the core,which looks different your support it will really boost up my project progress. plz help,its a mission mode project

entity MAC_v_2_1 is port( -- Clock signals

  ----------------------------
  gtx_clk                     : in  std_logic;
  tx_axi_clk_out              : out std_logic;
  
  -- Receiver Interface
  ----------------------------
  rx_axi_clk                  : in  std_logic;
  rx_reset_out                : out std_logic;
  rx_axis_mac_tdata  : out std_logic_vector(7 downto 0);
  rx_axis_mac_tvalid          : out std_logic;
  rx_axis_mac_tlast           : out std_logic;
  rx_axis_mac_tuser           : out std_logic;
  
rx_statistics_vector: out std_logic_vector(27 downto 0);
  rx_statistics_valid         : out std_logic;
  
  -- Transmitter Interface
  -------------------------------
  tx_axi_clk                  : in  std_logic;
  tx_reset_out                : out std_logic;
  tx_axis_mac_tdata  : in  std_logic_vector(7 downto 0);
  tx_axis_mac_tvalid          : in  std_logic;
  tx_axis_mac_tlast           : in  std_logic;
  tx_axis_mac_tuser           : in  std_logic;
  tx_axis_mac_tready          : out std_logic;      
  tx_retransmit               : out std_logic;
  tx_collision                : out std_logic;
  tx_ifg_delay : in  std_logic_vector(7 downto 0);

tx_statistics_vector: out std_logic_vector(31 downto 0); tx_statistics_valid : out std_logic;

  -- MAC Control Interface
  ------------------------
  pause_req                   : in  std_logic;
  pause_val        : in  std_logic_vector(15 downto 0);

  -- Current Speed Indication
  ---------------------------
  speed_is_10_100             : out std_logic;
  
  -- Physical Interface of the core
  --------------------------------
  gmii_txd         : out std_logic_vector(7 downto 0);
  gmii_tx_en                  : out std_logic;
  gmii_tx_er                  : out std_logic;
  gmii_rxd           : in  std_logic_vector(7 downto 0);
  gmii_rx_dv                  : in  std_logic;
  gmii_rx_er                  : in  std_logic;
  glbl_rstn                   : in  std_logic;
  rx_axi_rstn                 : in  std_logic;
  tx_axi_rstn                 : in  std_logic

); end MAC_v_2_1;

Hi Chandra,

I think you are trying to use the core directly. Xilinx provide an example design that wraps the core and provides a more usable mac layer interface. If you look at the example design directory that is generated with the core you will see this.

In particular, you should find that it contains a module called something like gmii_if_vx_y and you will see that this module (amongst other things) maps the GMII_TX_CLK and GMII_RX_CLK signals onto the GMII interface.

I recommend that you read the documentation that comes with the xilinx core and examine their example design.

Cheers, Peter

dear i have generated ip core.i am using some portion from example design and some from portion from your design i implemented using xv6mac_straight.vhd(did not use fifo based design). file name of MAC core generated is ethv_1_1.xco i am geting 1 warning during synthesis. " Line 173: <ethv_1_1> remains a black-box since it has no binding en "

will it create some problem?is there any issue related to ip core? if possible,plz give me your personal email id so that i can send you complete project to resolve the issues

Hi Chandra,

I dont know what "remains a blackbox" means, and I dont really have time to debug your code for you.

If it helps, I can send you a complete ISE working project for you to review. It is the one I used for the ML605 board.

If you would like that, please post your email address.

Regards, Peter

Dear sir, it will really help me if u send me complete ISE project. i am using ISE 13.1(embedded tri mode ethernet wrapper v2.1). my Email Address is cs_dwivedi@yahoo.co.in shekhar.chandra39@gmail.com thanks in advance

This is the Xilinx lan code?

Hi Dong,

This is the Xilinx lan code?

Not sure what you mean. This project has UDP/IP stack for 1G Ethernet. It has been used successfully on both Xilinx and Altera FPGAs.

Regards, Peter

Excuse me. could you send me a copy of the project?

mail: window1992@live.com

Hello dear,

Could you tell me how to implement this coding with Altera soft? We are using EP4C115I. Do you mind send me Quartus Project for us.

My email: charis@xcarbide.com

Thanks!

Charis

Hi Shekhar,

here is a sample Xilinx ISE project that may help you.

http://www.mediafire.com/download.php?pqbdpom9moqoa0b (19MB).

I tried your code in simulation it give the the error

"arp_layer is not declared" can you have any idea to remove the error? I tried all that i know but the error still comes.