1G eth UDP / IP Stack

In the following module, what is the synchroniser? Is it a Xilinx IP?

-- Component declaration for the reset synchroniser

component reset_sync_v2_2 port ( reset_in : in std_logic; -- Active high asynchronous reset enable : in std_logic; clk : in std_logic; -- clock to be sync'ed to reset_out : out std_logic -- "Synchronised" reset signal ); end component;

The Synchroniser is some code generated by the Xilinx V6EMAC 1G Eth MAC core wrapper. You find it in the example design created when you generate the core.

Hi Peter,

Thank you for the post. Your documentation about this core is very helpful. But, I have a problem because of the ISE version change. It seems to be that the generated EMAC core wrapper for version 2.1 (in ISE 13.2) and version 2.2 (in ISE 13.4) are different.

If you have, is it possible to upload (or email to samarawickrama@gmail.com) the xv6mac_straight.vhd for ISE 13.2 version (EMAC 2.1).

If you have a archive, please send me a ISE 13.2 project.

Thank you. Samarawickrama

Thank you for the sent link. By using mac_v2_1 folder and SVN v1.3, I could regenerate the project for ISE 13.2.

Mahendra reports that problem is now solved. Closing this bug.