OpenCores

ULPI Wrapper :: Overview



Project maintainers

Details

Name: ulpi_wrapper
Created: Dec 30, 2015
Updated: Jan 2, 2016
SVN Updated: Apr 23, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Communication controller
Language:Verilog
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD

Github: http://github.com/ultraembedded/cores

This IP core converts from the UTMI interface to the reduced pin-count ULPI interface. This enables interfacing from a standard USB SIE with UTMI interface to a USB 2.0 PHY.

This enables support of USB LS (1.5mbps), FS (12mbps) and HS (480mbps) transfers.

The design does not support low power mode.

All IOs are synchronous to the 60MHz ULPI clock input (sourced from the PHY), so care needs to be taken to configure the FPGA constraints to ensure the ULPI interface correctly meets timing.

References
Testing

Verified under simulation and also on a Xilinx FPGA connected to a SMSC/Microchip USB3300 in device mode using the USB3300 USB HS evaluation board.

The supplied testbench requires the SystemC libraries and Icarus Verilog, both of which are available for free.

Size / Performance

With the current configuration...

  • This design consumes around 88 LUTs on a Xilinx Spartan 6 with IOB packing for the outputs.
  • There are around 90 flops in the design.