This is a modular memory controller supporting different types of memories. Initial design will have support for SDR SDRAM. Upcoming releases will add support for DDR SDRAM and possibly other variants as well
The design is built with the following modules
The wishbone interface supports up to 8 independent interfaces where 4 are high priority real time ports
Dual async FIFO buffers
This design uses up to 8 outgoing and up to 8 incoming FIFO queues. On the outgoing channels control and data are transmitted and on the incoming read data is received. These are async FIFO supporting different clock domains for wishbine and memory side. FIFO implemenation is based on versatile_FIFO found on OpenCores.
SDR SDRAM controller
A state machine is used for communication to/from memories.