via6522
Project maintainers
Details
Name: via6522
Created: Jan 30, 2022
Updated: Jan 31, 2022
SVN Updated: Jan 31, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jan 30, 2022
Updated: Jan 31, 2022
SVN Updated: Jan 31, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: B.3
License: BSD
Language:Verilog
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: B.3
License: BSD
Description
via6522 is a register compatible rendition of the 6522 versatile interface adapter ic. However via6522 defaults to a 12-bit bus width and has an extra timer. via6522 is in use in the CmodA709 project under the rf6809 processor project.
The url of the svn repository is: https://opencores.org/websvn/listing/via6522/via6522
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