This combination should have resulted in a point to point connection but results in an unuseable/unsynthesizeable design.

In my case, 1 master and 1 slave resulted in an empty design debian linux unstable ii perl 5.8.8-7 Larry Wall's Practical Extraction and Report

cat >wishbone.defines <<...EOF...

Generated by PERL program wishbone.pl.

File used as input for wishbone arbiter generation

Generated Wed Feb 28 00:54:05 2007

filename=wb intercon=intercon syscon=syscon target=xilinx hdl=verilog signal_groups=0 tga_bits=2 tgc_bits=3 tgd_bits=0 rename_tga=bte rename_tgc=cti rename_tgd=tgd classic=000 endofburst=111 dat_size=8 adr_size=8 mux_type=andor interconnect=sharedbus

master wbm1 type=rw lock_o=0 tga_o=0 tgc_o=0 tgd_o=0 err_i=0 rty_i=0 priority=1 end master wbm1

slave wbs1 type=rw adr_i_hi=31 adr_i_lo=2 tga_i=0 tgc_i=0 tgd_i=0 lock_i=0 err_o=0 rty_o=0 baseadr=0x00000000 size=0x0000000f baseadr1=0x00000000 size1=0xffffffff baseadr2=0x00000000 size2=0xffffffff end slave wbs1 ...EOF... perl ../../opencores/cvs_by_webname/wb_builder/generator/wishbone.pl -nogui wishbone.defines

cat wb.v // Generated by PERL program wishbone.pl. Do not edit this file. // // For defines see wishbone.defines // // Generated Wed Feb 28 00:59:51 2007 // // Wishbone masters: // wbm1 // // Wishbone slaves: // wbs1 // baseadr 0x00000000 - size 0x0000000f

That is it. No code, just comments.

Adding another slave port does not fix the problem.

I tried to make a bus with one master and eight slaves connected via multiplexors. As I tried to compile the VHDL code there was an unknown signal named master1_bg which should grant the bus to master1. Since if there is only one master, there is no traffic control necessary, so the signal was not created. I solved the problem by simply deleting "and master1_bg" in every condition. "master1" was the name of my master. I also had problems using more than 8 masters or 8 slaves

Just found the same fault.

For VHDL created one master, one slave shared bus, and the signal wbm1_bg is not driven in the design but is used as an input in various other parts of the design.

I to deleted the signal wbm1_bg from the source, and the design compiled.

Anyone know perl ?

First solution: Replace all " le " with " <= " in the perl script (approx. 100 times)! And comment out line 1449.