Unneback, Michael

WISHBONE Builder

How can I upload my fixes, i repaired the bug with $* and signle master bus grand.

Fixed the $* and one master problems

Got the following on first run of the tool:

$* is no longer supported at wishbone.pl line 141.

This is perl 5, version 12, subversion 4 (v5.12.4) built for darwin-thread-multi-2level

$* is no longer supported at wishbone.pl

I have a simple Wishbone system with one master and two slaves.  One slave has a baseaddress of 0xf7810000 and a size of 0x00000100, and the slave select of this slave in the generated VHDL file is:

P2020_SPI_ss <= '1' when P2020_adr_o(31 downto 8)="" else 
'0';

Could someone look into this?  Thanks.

Address decoding sometimes does not work

According to the Wishbone spec: "A SLAVE shall
respond to other WISHBONE signals only when this [STB_I] is asserted."

Therefore, the bus arbiter should gate the stb_i signals for slave devices to ensure that only the one being addressed responds to the cycle. 

The code generated by this script instead gates the cyc_i slave signals. It is therefore incompatible with some Wishbone compliant modules, for example the register banks provided in the Wishbone toolkit package, as these expect the strobe signal to be gated rather than cyc.

I can check in a fix if nobody else is currently working on the module. It is a simple change to the script - instead of assigning the slave_stb_i signals to stb, assign them to stb & slave_ss (where slave_ss is the select signal for that slave device). 

There may be a little more to it to ensure this works with all the supported bus topologies.

Regards,
Richard Walker.

Address decoder should gate stb signals, not cyc signals.

Although I haven't verified that this is the case in all modes, the script as it stands writes invalid VHDL when creating the address decoders (in the VHDL decoder block).

The problem is due to the use of a string comparison operator (ge) instead of a numeric comparison (>=) on line 1387. With this changed, it works perfectly!

I'm not sure what success other people are having with this module, maybe it works in other configurations? I have 2 masters, 2 slaves, and AND/OR shared bus logic.

Good job though. I'm willing to check in the fix if nobody objects...

Regards,
Richard.

Address decoding doesn't work

As I read B3 of the wishbone specification, page 16, fig 1.2, shows a Wishbone master connected to a wishbone slave.

It shows the out ports of the master connected to the in ports of the slave, and the out ports of the slave connected to the in ports of the master.

But, this perl code produces a scrambled bus.

e.g. in the perl
wbm1_dat_i , is defined as an output in the vhdl. whilst
wbs1_dat_o, is defined as an input in the vhdl.

WB master data in and out wrong way round

This combination should have resulted in a point to point connection but results in an unuseable/unsynthesizeable design.

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