WISHBONE Builder

As I read B3 of the wishbone specification, page 16, fig 1.2, shows a Wishbone master connected to a wishbone slave.

It shows the out ports of the master connected to the in ports of the slave, and the out ports of the slave connected to the in ports of the master.

But, this perl code produces a scrambled bus.

e.g. in the perl wbm1_dat_i , is defined as an output in the vhdl. whilst wbs1_dat_o, is defined as an input in the vhdl.

The generated intercon module is for interconnecting Wishbone master and slave modules outside of the intercon module itself. So the ports are defined the way ther are now.