WISHBONE Builder

Although I haven't verified that this is the case in all modes, the script as it stands writes invalid VHDL when creating the address decoders (in the VHDL decoder block).

The problem is due to the use of a string comparison operator (ge) instead of a numeric comparison (>=) on line 1387. With this changed, it works perfectly!

I'm not sure what success other people are having with this module, maybe it works in other configurations? I have 2 masters, 2 slaves, and AND/OR shared bus logic.

Good job though. I'm willing to check in the fix if nobody objects...

Regards, Richard.

Yes, I just figured this out for myself. It is not just one line though. 1387, 1400, 1414, and 1428 all have the same problem. After the fix it works perfectly.

And it clearly a programming error because "ge" does not make any sense.