Wishbone DDR3 SDRAM Controller

Sep 17, 2016	Simulation works for a 4:1 command multiplexing.	Gisselquist, Dan
Sep 2, 2016	Chatted w/ Digilent and Xilinx. Need to slow the memory logic clock down to 80MHz from 200MHz.	Gisselquist, Dan
Aug 23, 2016	More updates. Tried to connect it to I/O ports today, checked in my work, but it isn't working yet.	Gisselquist, Dan
Aug 19, 2016	The simulation now works (again) with the new parameters.	Gisselquist, Dan
Aug 18, 2016	Recalibrating ... again! (DDR1333 memory, not DDR1600)	Gisselquist, Dan
Aug 16, 2016	Trying to recover, and (mostly) starting over. Posted some pictures on the status page.	Gisselquist, Dan
Aug 5, 2016	Updated page to point out massive clock/timing error, indicate hints at a better redesign.	Gisselquist, Dan
Aug 3, 2016	Daily status update.	Gisselquist, Dan
Aug 1, 2016	It works in the simulator.	Gisselquist, Dan
Jul 31, 2016	Status update	Gisselquist, Dan
Jul 30, 2016	Controller works through the initial write command, although it doesn't yet complete it.	Gisselquist, Dan
Jul 28, 2016	Added initial description to project.	Gisselquist, Dan

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