X.25 interface core

Description

X.25 interface core is designed to separate data and signaling component from an X.25 format data frame. As other protocols do, X.25 consists of several fields, which can be divided into Signaling Part and Data Part. Not all X.25 data frames contain data fields, for some frames are used for maintaining communication, error and flow control, etc. The aim of this interface core is to recognize data part regardless the types of the frames.

In this project, the input is simulated by generating input bitstream from testbench. Some issues which comes up are bit stuffing, which have to be eliminated before processing, and have to be inserted before sending the result back into bitstream forms.

Features

Technical specification:
- frames which are able to be processed:
- basic packet configuration (modulo 8)
- single link procedures
- multi link procedures (transfer rate on 64 Kbps)
- maximum data user allowed is 128 bytes

Functional specication:
- recognize data field regardless various types of frames, so the data can be altered without changing any signaling part
- eliminate stuffed bits in the input frames, and generate stuffed bits after the frame is processed

Status

- phase: Design done, FPGA proven
- Development: Alpha
- (contact me for the souce codes and documentations. free.)