xgate

May 21, 2012	The RTL has been stable for quite some time so upgrade the status from planning alpha	Hayes, Robert
Aug 12, 2010	Applications - The first application code added is the SKIPJACK encrypt/decrypt function. This algorithm works on a 64 bit block of data and uses an 80 bit key. See the sw/applications/skipjack/README.txt file for more information. Testbench - To aid in software development a simple debug module was added to the testbench. The debugger loads watchpoint addresses stored in RAM after the first RAM initialization. The debugger generates trigger signals that can be watched in the waveform viewer and captures a copy of the CPU registers at each trigger event. There are enable registers in the testbench that can enable or disable any of the eight individual watchpoints under testbench control. Doc - Made corrections to some of the example code in the detailed instruction descriptions.	Hayes, Robert
Jun 10, 2010	Added descriptions for interrupt bypass registers. Added Appendix B for testbench description. Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, missing default on shifter lines 2382 (Although all cases are covered). Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and input pins along with assoicated status and and control registers. This channel has never been usable. Added new control registers for interrupt bypass function. Out of reset all input interrupts are bypassed directly to the Xgate interrupt outputs. The interrupts are also disabled from effecting the Xgate till the bypass is disabled. The interrupt priority has been flipped so that now the lowest index input interrupt has the highest priority.	Hayes, Robert
Apr 22, 2010	Fixed errors related to entering DEBUG mode when RAM access wait states are enabled. See the README in the "trunk" directory for more details about these changes and others made since January.	Hayes, Robert
Jan 27, 2010	Fixed error in wbs_ack_o signal when Xgate wait states were enabled. Changes were made to the WISHBONE master bus interface and the RISC control logic. Instruction set details added to the documentation. See the README in the "trunk" directory for more details about these changes and others made since October.	Hayes, Robert
Oct 7, 2009	Oct 07,2009 RTL - 85% done All debug commands now working, including writes to XGCHID register. Updates to testbench, added timeout and total error count. Updates to User Guide. Created the sw directory and copied over the software stuff from the bench directory.	Hayes, Robert
Oct 7, 2009	SVN update, News update	Hayes, Robert
Sep 10, 2009	Sept 10,2009 Added WISHBONE master bus submodule and some related top level signals but still not much real functionality. Added code to allow for memory access stalls. Upgraded testbench to insert memory wait states. Added more error detection and summery. Improved instruction decoder. Still needs more work to remove redundant adders to improve synthesis results.	Hayes, Robert
Sep 2, 2009	Sept 1, 2009 This is a prerelease checkin and should be looked at as an incremental backup and not representative of what may be in the final release. RTL - 75% done What works: Basic instruction set execution simulated and verified. Condition code operation on instructions partially verified. Basic WISHBONE slave bus operation used, full functionality not verified. What's broken or unimplemented: All things related to debug mode. WISHBONE master bus interface. User Documentation - 30% done	Hayes, Robert

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