Ethernet 10GE MAC
News
| Nov 26, 2012 | Timing improvements. Reduced FIFO size from 1024 to 512 bytes | Tanguay, Andre |
| Nov 25, 2012 | Added basic packet statistics | Tanguay, Andre |
| Nov 24, 2012 | Update comments | Tanguay, Andre |
| Nov 23, 2012 | Improved design for timing, eliminating chained adders | Tanguay, Andre |
| Nov 23, 2012 | Added alternate FIFO design for Xilinx | Tanguay, Andre |
| Feb 17, 2012 | Added release notes | Tanguay, Andre |
| Feb 8, 2012 | Update feature list | Tanguay, Andre |
| Feb 8, 2012 | Updates for Xilinx synthesis | Tanguay, Andre |
| Jan 19, 2012 | Added latency numbers to feature list | Tanguay, Andre |
| Aug 20, 2011 | Updates to future devel. | Tanguay, Andre |
| Dec 13, 2009 | New SERDES examples to 10GE MAC | Tanguay, Andre |
| Jun 7, 2008 | Changes commited to CVS | Tanguay, Andre |
| May 19, 2008 | Project started | Admin, OpenCores |
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