Nov 26, 2012Timing improvements. Reduced FIFO size from 1024 to 512 bytesTanguay, Andre
Nov 25, 2012Added basic packet statisticsTanguay, Andre
Nov 24, 2012Update commentsTanguay, Andre
Nov 23, 2012Improved design for timing, eliminating chained addersTanguay, Andre
Nov 23, 2012Added alternate FIFO design for XilinxTanguay, Andre
Feb 17, 2012Added release notesTanguay, Andre
Feb 8, 2012Update feature listTanguay, Andre
Feb 8, 2012Updates for Xilinx synthesisTanguay, Andre
Jan 19, 2012Added latency numbers to feature listTanguay, Andre
Aug 20, 2011Updates to future devel.Tanguay, Andre
Dec 13, 2009New SERDES examples to 10GE MACTanguay, Andre
Jun 7, 2008Changes commited to CVSTanguay, Andre
May 19, 2008Project startedAdmin, OpenCores