Zip Cpu
News
| May 24, 2017 | Updated the honesty page to match the 2.0 version of the process that came up some time ago. | Gisselquist, Dan |
| Feb 11, 2017 | Updated the project page with info on the 8-bit byte branch on GitHub. | Gisselquist, Dan |
| Dec 6, 2016 | General site cleanup, provide pointer to GitHub page, etc. | Gisselquist, Dan |
| Jul 17, 2016 | Adjusted the honest assessment to indicate the removal of the LDIHI instruction, and the creation of the 32x32 bit MPY instruction(s). | Gisselquist, Dan |
| May 30, 2016 | Updating the project page to note where a copy of the ZipOS may be found. | Gisselquist, Dan |
| Apr 13, 2016 | Updating the project page with changes that have taken place to the processor. | Gisselquist, Dan |
| Mar 25, 2016 | Announcing the existence of a GCC compiler port! | Gisselquist, Dan |
| Jan 28, 2016 | A binutils backend is now available for the Zip CPU. (Early branching has also been simplified.) | Gisselquist, Dan |
| Dec 29, 2015 | Fixing instruction set documentation. | Gisselquist, Dan |
| Dec 22, 2015 | (Still updating pages with the instruction set updates ... 30 minutes wasn't enough time.) | Gisselquist, Dan |
| Dec 22, 2015 | The new Instruction Set is now available for the Zip CPU. Please see the Instruction set page for details. | Gisselquist, Dan |
| Dec 14, 2015 | Updated the current status (main page) to reflect the existence of a new instruction set, as well as an improved cache. I expect to the updates within the next couple of weeks. | Gisselquist, Dan |
| Nov 4, 2015 | Updating the project assessment page. | Gisselquist, Dan |
| Oct 22, 2015 | Simplified logic, down to 1040 LUTs minimum. Also added bus error detection in the prefetch module, better error handling, fixed jump instruction in the assembler, and more. | Gisselquist, Dan |
| Oct 12, 2015 | Still making updates | Gisselquist, Dan |
| Oct 12, 2015 | Usage numbers updated to reflect the existence of a 953 LUT build with pipelined instructions. | Gisselquist, Dan |
| Oct 4, 2015 | Some updated notes on the honest assessment--it's not as bad as it was. | Gisselquist, Dan |
| Sep 30, 2015 | Added a description of the Zip Bones package, together with the current status of the project. | Gisselquist, Dan |
| Sep 29, 2015 | (Minor spelling edits) | Gisselquist, Dan |
| Sep 29, 2015 | Adjusted the "honest assessment" to reflect that fact that the Zip CPU can now do pipelined loads and stores on the wishbone bus. | Gisselquist, Dan |
| Sep 21, 2015 | Still updating the web page. | Gisselquist, Dan |
| Sep 21, 2015 | Updating project pages with text from the updated spec. | Gisselquist, Dan |
| Sep 11, 2015 | Still updating the web page. | Gisselquist, Dan |
| Sep 11, 2015 | Still updating the web page. | Gisselquist, Dan |
| Sep 11, 2015 | Adding an "Honest assessment" of how well the Zip CPU has fulfilled its goals, and where the project may need to go next. | Gisselquist, Dan |
| Sep 4, 2015 | Updating documentation. | Gisselquist, Dan |
| Sep 3, 2015 | Updated the LUT count with the results from adding the DMA in place of the useless manual cache. Further updates replacing and getting rid of the manual cache have not yet been checked in. | Gisselquist, Dan |
| Aug 28, 2015 | Minor change to the project page. | Gisselquist, Dan |
| Aug 27, 2015 | Fixed the broken link to Dr. Sauerman's O/S book. | Gisselquist, Dan |
| Aug 24, 2015 | Updated the LUT count (last paragraph of opening page) with the most recent changes, following pipeline streamlining. | Gisselquist, Dan |
| Aug 22, 2015 | Still updating the web page. | Gisselquist, Dan |
| Aug 22, 2015 | Updating the instruct set architecture page with reset changes, including the addition of a 'trap' bit to the condition codes and multiply signed and unsigned instructions. | Gisselquist, Dan |
| Aug 17, 2015 | Added a comparison between the Zip CPU ISA and the RISC-V ISA used by lowRISC. | Gisselquist, Dan |
| Aug 17, 2015 | Added a bus description to the instruction set page. | Gisselquist, Dan |
| Aug 16, 2015 | I added the basics of a debugger to the project. The debugger works, but needs to be instantiated on hardware so it won't build in its posted configuration. | Gisselquist, Dan |
| Aug 12, 2015 | After a lot of work, I have now checked in the new assembler. It's still not a polished and finished product, but it does successfully assemble our regression test/assembly file. | Gisselquist, Dan |
| Aug 9, 2015 | Adjusted the project page to help document why I am building the Zip CPU. | Gisselquist, Dan |
| Aug 9, 2015 | The assembler has now undergone a major upgrade. While not yet submitted to CVS, since the upgrade isn't complete yet, the new assembler is a flex/bison creation that can now handle jump to labels within the code. | Gisselquist, Dan |
| Jul 28, 2015 | As of this morning, the core runs on a Basys-3 board and passes its watch-dog timer test. (Many more tests to follow ...) | Gisselquist, Dan |
| Jul 27, 2015 | Updating the instruction set table to match how the CPU is currently built. (Specifically, the ROL instruction.) | Gisselquist, Dan |
| Jul 27, 2015 | Changed the colors on the Zip System diagram to match the diagram in the documents folder. | Gisselquist, Dan |
| Jul 26, 2015 | Still building the project page. | Gisselquist, Dan |
| Jul 26, 2015 | Still introducing the project page. | Gisselquist, Dan |
| Jul 26, 2015 | First initial upload of the project. | Gisselquist, Dan |
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